Typical Design Flow in V-L-S-I

• Specification: Word, Frame Maker.
  
• High Level Design: Word, Frame Maker, Timing tools, Visio.
  
• Micro Design/Low level design:Word, Frame Maker, Timing tools, Visio.
  
• RTL Coding : Vim, Active HDL editor, Em-editor.
  
• Simulation : Modelsim, VCS, Verilog-XL.
• Synthesis : Design Compiler, FPGA Compiler, Synplify, Leonardo Spectrum. You can download this from FPGA vendors like Altera and Xilinx for free.
• Place & Route : For FPGA use FPGA' vendors P&R tool. ASIC tools require expensive P&R tools like Apollo. Students can use LASI, Magic.
• Post Si Validation : For ASIC and FPGA, the chip needs to be tested in real environment. Board design, device drivers needs to be in place.