Gate level simulation

With wide acceptance of STA and Formal verification tools by the industry one question still arises in the minds of many, "Why do we need gate level simulation?"
The common reasons quoted by many engineers are simple..

1. To check if reset release, initialization sequence and boot-up is proper.
2. Since Scan insertions occur during and after synthesis, they are not checked by simulations.
3. STA does not analyze asynchronous interfaces.
4. Unwanted usage of wild cards in static timing constraints set false and multi cycle paths where they dont belong. This can also be due to design changes, mis-understanding or typos.
5. Usage of create_clock instead of using create_generated_clock between clock domains.
6. For switching factor to estimate power.
7. X's in RTL sim can be pessimistic or optimistic. Any unintended dependencies on initial conditions can be found through GLS.
8. Design changes, wrong understanding of the design can lead to incorrect false paths or multicycle paths in the constraints.
   
9. Can be used to study the activity factor for power estimation.
10. It's an excellent feel good quotient that the design has been implemented correctly.

Some design teams use GLS only in a zero-delay, ideal clock mode to check that the design can come out of reset cleanly or that the test structures have been inserted properly. Other teams do fully back annotated simulation as a way to check that the static timing constraints have been set up correctly.

In all cases, getting a gate level simulation up and running is generally accompanied by a series of challenges so frustrating that they precipitate a shower of adjectives as caustic as those typically directed at your most unreliable internet service provider. There are many sources of trouble in gate level simulation. This series will look at examples of problems that can come from your library vendor, problems that come from the design, and problems that can come from synthesis. It will also look at some of the additional challenges that arise when running gate level simulation with back annotated SDF.

Metastability

Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability.

AHB Specification - Few points

What is the concept of global hready?
When Core act as Slave:
1. Slave should check only t_hready_glb during the address phase. (No need to consider t_hready in address phase).

2. Slave should check only t_hready during data phase. (No Need to consider t_hready_glb in data phase).

When Core act as Master:
Master should consider only m_hready (currently addressed target's hready) in both address and data phase. No need to consider t_hready_glb in both address and data phase.


Is HREADY an input or an output from slaves?
From ARM Website:
Applies to: AMBA AHB

An AHB slave must have the HREADY signal as both an input and an output.

HREADY is required as an output from a slave so that the slave can extend the data phase of a transfer.

HREADY is also required as an input so that the slave can determine when the previously selected slave has completed its final transfer and the first data phase transfer for this slave is about to commence.

Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY input.


Explain the concept of Retry and Split in AHB?
Lets say the master is doing 4beat transaction. For the first data phase, the slave sends OK response, and for the second data phase the slave sends split/retry response. For both retry and split, the master has to do the new transaction for 3Dwords, because only first Dword sent successfully in first data phase. So here the burst size will change. Because the master initiated with 4beat burst and because of split/retry response, only one DWORD is sent successfully and the master has to do the remaining 3 Dwords in Single transfers (new transactions). So it is recommended for the slave to send split or retry only during first data phase, so that the master can retry the entire 4beat transaction again (instead of changing the burst size for the remaining transactions).

The main difference between split and retry is,
For retry, the arbiter will send the grant whenever the master request for a bus, whereas
For split, the arbiter will assert the grant only when slave sends hsplit to the master.

Which is the only active low signal in AHB?
HRESETn is the only active low signal in AHB.

Does AHB supports address bus more than 32 bits?
No, AHB supports only 32 bit address bus.

What is maximum data width of an AHB bus?
AHB supports data width from 8 bits to 1024 bits.

How many Master/Slave can be connected?
We can connect maximum of 16 Master/Slave.

Why the boundary cross is set to 1K in AHB protocol?

It is possible for AHB to operate with a small memory
region partitioning, however, doing so might have a
number of potential problems:
1. the fan out of lower address bit in the system-on-chip design might be quite high. Connecting those bits to the AHB decoder might badly affect bus performance (max freq) and power consumption.

2. a long burst might end up going across two devices, as a result the first transfer going to the second device could become a SEQ transfer, hence breaking the AHB protocol.

3. AMBA system design software from various vendors might not support memory boundary less tan 1kB.

I got the above reply from,

http://newsgroups.derkeiler.com/Archive/Comp/comp.sys.arm/2006-04/msg00044.html


I hope the second point is strong point to have the boundary as 1kB for AHB.


Another one... found in ARM Forum
http://forums.arm.com/index.php?showtopic=12840


And another one...
http://www.velocityreviews.com/forums/t298804-ahb-protocol-document-clarification.html

If a master bursted across a 1K boundary (i.e. into the next page)
---> the first slave might or might not remain selected and
---> the second slave might or might-not pick up selection
(it really shouldn't though even if it's HSEL = 1 when HTRANS != NSEQ)

Can the bus master cancel a transfer it has started?
No provision is made within the AHB specification for a bus master to cancel a transfer once it has commenced.

How many wait states a slave insert?
It is recommended, but not mandatory, that slaves do not insert more than 16 wait states to prevent any single access locking bus for a large number of clock cycles.

Where can I find more questions related to AHB?
Here is the link for Frequently Asked Questions to AHB

Typical Design Flow in V-L-S-I

• Specification: Word, Frame Maker.
  
• High Level Design: Word, Frame Maker, Timing tools, Visio.
  
• Micro Design/Low level design:Word, Frame Maker, Timing tools, Visio.
  
• RTL Coding : Vim, Active HDL editor, Em-editor.
  
• Simulation : Modelsim, VCS, Verilog-XL.
• Synthesis : Design Compiler, FPGA Compiler, Synplify, Leonardo Spectrum. You can download this from FPGA vendors like Altera and Xilinx for free.
• Place & Route : For FPGA use FPGA' vendors P&R tool. ASIC tools require expensive P&R tools like Apollo. Students can use LASI, Magic.
• Post Si Validation : For ASIC and FPGA, the chip needs to be tested in real environment. Board design, device drivers needs to be in place.