Points and topics to be covered before an interview

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Read Basic electronics and digital concepts
Combinational circuits (Basic gates, Mux, Adder, Multiplier and Encoder ...)
Sequential circuits (Latch, Flip flop, State machine and Counter ...)
Memories (Single, Dual, Quad port RAM and ROM)
MOS, CMOS, NMOS and PMOS techniques

Read all Cliff Cummings free papers

Read about Verilog language
Diff b/w tasks and functions
Diff b/w blocking and non blocking
Diff b/w various delays
Full and Parallel case
Diff b/w casex and casez
Diff b/w === and ==
Diff b/w logical && and bitwise &
Diff b/w bitwise, unary, logical operators
Diff b/w blocking and non blocking operator
Diff b/w always and initial
Diff b/w procedural and continuous assignment
Can task/function is synthesizable?
Can for/repeat/while loop is synthesizable?
Can fork join is synthesizable?


Read about VHDL language
Diff b/w signals and variables
Diff b/w functions and procedures

Read RMM Guidelines

Read synthesis concepts

Read Timing simulation and techniques

Read below listed concepts and topics
Clock dividers
Reset synchronizer
Clock and Reset tree
Clock Skew, Clock fidelity, Clock Jitter
Cross talk
Synchronization techniques - Handshake, Double flop, Three flop, Pulse, Level and FIFO based
DFT
BIOS
BIST
Timing
CPLD, FPGA and ASIC
FIFO and RAM
Gate level netlist
SDF
Low power design techniques
Pipe line design
Static and Dynamic timing analysis
FIFO depth calculation
Setup and Hold time, Clock to Q, Pin-to-pin and propagation delay
Metastability
Maximum frequency formula
Inertial, Transport and various delays
Mealy and Moore FSM
Binary and One hot encoding
Binary and Gray pointers
Master and Slave DMA
Arbitration techniques – Round robin, Weighted Round robin, Programmable weighted round robin, Priority, Circular etc.,
Various timing delays
Synchronous and Asynchronous clocks
Synchronous and Asynchronous resets
Latch and Flop
Multi cycle and False path
Glue logic
PLL

General technical questions
How will you start code a RTL?
What are the general coding guide lines/styles you followed?
Tell us the tools you have been working?
How your test environment looks?
Once you have done the RTL code, does your work end? What will you do next?

Read PERL language

Read PLI generation and usage

Read all the Tools and Analyzers you worked

Read all the protocol specifications you are in familiar
List out the important terms and points in the specifications

Take care of the below designs
Multi clock design
FIFO design
Various RAMs

General questions asked by an interviewer
Tell us about your self
Tell us about your current project
Which one you are interested in? Design or Verification?
Have you involved in verification?
Why are you leaving the current company?
What is your expected salary?
Do you have any offers from other company?
Are you actively participating this interview?
Are you ready to relocate to our company located in “SOME” place?
Do you have any questions?