Design for Verification

Messaging is a nice concept of displaying useful information during simulation. These
messages can be used to convey wide range of severity levels.

Considerations for implementing messaging
------------------------------------------------
Identify the level of message in terms of severity
Controllability of the message
Timestamp of the message
Message Identification

Different kind of severity levels
------------------------------------------
INFO: Message is simply an information
WARNING: Something unusual happen but no need to stop simulation
ERROR: Indicates that something is wrong and you need to debug and find out
the root cause and fix it
FATAL: Displayed when there is a serious issue. Simulation will immediately
terminate after displaying this message

What is BFM?
-------------------
Provides visibility into its communication processes at each level of abstraction
Visibility into all configurable parameters
Commanded to perform specified sequence of commands

Consideration for designing BFM
-------------------------------------------
Map the hierarchy of protocol or functionality into BFM
Provide a built-in self check capability
Specify all the key variables in one single file
Ensure all configurable variables must have defaults
Must provide a provision to filter the messages
All the inputs to the tasks/commands within the BFM should be checked for legal
ranges.
Must provide a provision for message ID

Typical flow for designing BFM
------------------------------
Specify the abstraction level at which the BFM is planned to be used
Specify user level configuration parameters
Specify the hierarchy of commands when they are functionally dependent on
hierarchical fashion
Specify the commands that user will be able to call within the BFM
Specify the details of the message that BFM should convey
Specify the interface ports that the BFM use to interact with the DFT
Make sure to display the value of parameters before the simulation starts
Provide a provision to log the BFM messages into a file or standard output
Provide a checking mechanism to check the legal range of all the parameters and
input value

Main functions of a bus monitor
=--------------------------------------
Protocol checking
*****************
Violation of protocol
Monitoring for X and Z values on signals
Design latencies between critical signals
Monitor timing violations such as setup and hold

Transaction logging
*******************
Log the message with severity level, ID, and description
Provide the option to display them as standard output or in a file

CVS

Computer Vision Syndrome (CVS)

Recent studies have shown that about 85 per cent of computer users suffer from computer vision syndrome

Computer Vision Syndrome (CVS) is a complex eye and vision-related problem associated with computer use. Recent studies have shown that about 85 per cent of computer users suffer from this problem, possibly making it the silent epidemic of the 21st century.

Hence it is important to know a few essential things about CVS.

Symptoms

The primary symptoms are eyestrain, blurred vision, dry and irritated eyes, tired eyes, and headaches. Neck and backaches can also be related to the way we use our eyes at the computer.

Causes

There are several reasons, but the most important reason is that the blink rate (16 / min) is reduced to about 1/3 the normal rate. This leads to irritation, dryness, excessive tearing, burning, itching and redness.

Contact lens wearers also often experience problems with their contact lenses. In response, reflex tearing sometimes occurs and floods the eyes with tears.

Precautions

Use artificial tears to rewet and lubricate your eyes. Lower the computer screen so that the centre of the screen is four to eight inches below your eyes. If seated in a draft or near an air vent, try to eliminate the flow of air past your eyes.

Low humidity or fumes aggravate a dry eye condition, so fix these if possible. Blink whenever you begin to sense eye discomfort; close eyelids and roll eyes frequently.

While working on computers, use glasses with anti-reflection coating. These are advised for those wearing lens as well. For those with presbyopia (glasses for reading after 40 years), the best solution is a lens that is specifically designed for this purpose.

Because the eyes lead the body, the body will assume whatever position is required to enable your eyes to see comfortably. The most optimum viewing distance is considered to be 20-28 inches.

Care for eyes

Care of a person with CVS often requires an expanded case history, testing of the eyes or vision, or treatment since it involves taking into consideration many aspects.

Perfect computer display

Flat panel (LCD) are better than cathode ray tube (CRT) displays since they do not flicker and the contrast is typically higher. Optimal contrast and visibility are attained with black characters on a white background.

The size of the text should be three times the size of the smallest text you can read. Adjust refresh rate (flicker) as high as possible, preferably 85 hertz or higher. For colour monitors, smaller dot pitches (less than 0.28 mm) are desirable.

Adjust the screen contrast so that the characters are clear. Reflections from your computer screen reduce the contrast and make it difficult to see your work. If possible, remove the offending source of light - turn off the source, draw blinds and :

Know the best lighting

Bright lights or other bright objects in your peripheral vision are uncomfortable and can contribute to eye and musculoskeletal symptoms.

* Try the following measures.
* Turn off the light that is bothering you.
* If window light is causing discomfort, draw blinds.
*
Alter your workstation position so that bright overhead lights or bright windows are not in your field of vision. If a desk lamp is causing discomfort, try turning if off and determine whether you can still adequately see your work.
* Use a shield or partition to block bright lights.

Blurring of vision

Intermittent blurring is caused by an inability of the accommodative mechanism to maintain a steady focus on near objects.

This occurs when, after extended near work, the muscles remain fixed or somewhat locked in the near contracted position, effectively making the eye myopic, taking a few seconds to focus on objects. Sometimes this can last for several hours.

This can even affect driving and can be treated with spectacles and exercises. Eyelids flutter or twitch because the muscle surrounding the eye is fatigued. Take periodic breaks, eliminate glares and consider an eye examination.

There is no way that screen and the keyboard can be optimally located with laptops and notebooks and extended work is not recommended on these.

The author is cornea and refractive surgeon, Narayana Netralaya, Bangalore.
Computer Vision Syndrome (CVS)

Types of RAM

Gate level simulation

With wide acceptance of STA and Formal verification tools by the industry one question still arises in the minds of many, "Why do we need gate level simulation?"
The common reasons quoted by many engineers are simple..

1. To check if reset release, initialization sequence and boot-up is proper.
2. Since Scan insertions occur during and after synthesis, they are not checked by simulations.
3. STA does not analyze asynchronous interfaces.
4. Unwanted usage of wild cards in static timing constraints set false and multi cycle paths where they dont belong. This can also be due to design changes, mis-understanding or typos.
5. Usage of create_clock instead of using create_generated_clock between clock domains.
6. For switching factor to estimate power.
7. X's in RTL sim can be pessimistic or optimistic. Any unintended dependencies on initial conditions can be found through GLS.
8. Design changes, wrong understanding of the design can lead to incorrect false paths or multicycle paths in the constraints.
   
9. Can be used to study the activity factor for power estimation.
10. It's an excellent feel good quotient that the design has been implemented correctly.

Some design teams use GLS only in a zero-delay, ideal clock mode to check that the design can come out of reset cleanly or that the test structures have been inserted properly. Other teams do fully back annotated simulation as a way to check that the static timing constraints have been set up correctly.

In all cases, getting a gate level simulation up and running is generally accompanied by a series of challenges so frustrating that they precipitate a shower of adjectives as caustic as those typically directed at your most unreliable internet service provider. There are many sources of trouble in gate level simulation. This series will look at examples of problems that can come from your library vendor, problems that come from the design, and problems that can come from synthesis. It will also look at some of the additional challenges that arise when running gate level simulation with back annotated SDF.

Metastability

Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability.

AHB Specification - Few points

What is the concept of global hready?
When Core act as Slave:
1. Slave should check only t_hready_glb during the address phase. (No need to consider t_hready in address phase).

2. Slave should check only t_hready during data phase. (No Need to consider t_hready_glb in data phase).

When Core act as Master:
Master should consider only m_hready (currently addressed target's hready) in both address and data phase. No need to consider t_hready_glb in both address and data phase.


Is HREADY an input or an output from slaves?
From ARM Website:
Applies to: AMBA AHB

An AHB slave must have the HREADY signal as both an input and an output.

HREADY is required as an output from a slave so that the slave can extend the data phase of a transfer.

HREADY is also required as an input so that the slave can determine when the previously selected slave has completed its final transfer and the first data phase transfer for this slave is about to commence.

Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY input.


Explain the concept of Retry and Split in AHB?
Lets say the master is doing 4beat transaction. For the first data phase, the slave sends OK response, and for the second data phase the slave sends split/retry response. For both retry and split, the master has to do the new transaction for 3Dwords, because only first Dword sent successfully in first data phase. So here the burst size will change. Because the master initiated with 4beat burst and because of split/retry response, only one DWORD is sent successfully and the master has to do the remaining 3 Dwords in Single transfers (new transactions). So it is recommended for the slave to send split or retry only during first data phase, so that the master can retry the entire 4beat transaction again (instead of changing the burst size for the remaining transactions).

The main difference between split and retry is,
For retry, the arbiter will send the grant whenever the master request for a bus, whereas
For split, the arbiter will assert the grant only when slave sends hsplit to the master.

Which is the only active low signal in AHB?
HRESETn is the only active low signal in AHB.

Does AHB supports address bus more than 32 bits?
No, AHB supports only 32 bit address bus.

What is maximum data width of an AHB bus?
AHB supports data width from 8 bits to 1024 bits.

How many Master/Slave can be connected?
We can connect maximum of 16 Master/Slave.

Why the boundary cross is set to 1K in AHB protocol?

It is possible for AHB to operate with a small memory
region partitioning, however, doing so might have a
number of potential problems:
1. the fan out of lower address bit in the system-on-chip design might be quite high. Connecting those bits to the AHB decoder might badly affect bus performance (max freq) and power consumption.

2. a long burst might end up going across two devices, as a result the first transfer going to the second device could become a SEQ transfer, hence breaking the AHB protocol.

3. AMBA system design software from various vendors might not support memory boundary less tan 1kB.

I got the above reply from,

http://newsgroups.derkeiler.com/Archive/Comp/comp.sys.arm/2006-04/msg00044.html


I hope the second point is strong point to have the boundary as 1kB for AHB.


Another one... found in ARM Forum
http://forums.arm.com/index.php?showtopic=12840


And another one...
http://www.velocityreviews.com/forums/t298804-ahb-protocol-document-clarification.html

If a master bursted across a 1K boundary (i.e. into the next page)
---> the first slave might or might not remain selected and
---> the second slave might or might-not pick up selection
(it really shouldn't though even if it's HSEL = 1 when HTRANS != NSEQ)

Can the bus master cancel a transfer it has started?
No provision is made within the AHB specification for a bus master to cancel a transfer once it has commenced.

How many wait states a slave insert?
It is recommended, but not mandatory, that slaves do not insert more than 16 wait states to prevent any single access locking bus for a large number of clock cycles.

Where can I find more questions related to AHB?
Here is the link for Frequently Asked Questions to AHB

Typical Design Flow in V-L-S-I

• Specification: Word, Frame Maker.
  
• High Level Design: Word, Frame Maker, Timing tools, Visio.
  
• Micro Design/Low level design:Word, Frame Maker, Timing tools, Visio.
  
• RTL Coding : Vim, Active HDL editor, Em-editor.
  
• Simulation : Modelsim, VCS, Verilog-XL.
• Synthesis : Design Compiler, FPGA Compiler, Synplify, Leonardo Spectrum. You can download this from FPGA vendors like Altera and Xilinx for free.
• Place & Route : For FPGA use FPGA' vendors P&R tool. ASIC tools require expensive P&R tools like Apollo. Students can use LASI, Magic.
• Post Si Validation : For ASIC and FPGA, the chip needs to be tested in real environment. Board design, device drivers needs to be in place.

List of useful ACRONYM's

ARM
Architecture Reference Manual
Advanced RISC Machines
Acron RISC Machines Ltd.,

RISC - Reduced Instruction Set Computer chip

AMBA - Advanced Microcontroller Bus Architecture

AHB - Advanced High performance Bus
ASB - Advanced System Bus
APB - Advanced Peripheral Bus

AXI - Advanced eXtensive Interface

This post will be updated frequently......

Links from Mississippi State University

University Link - http://www.ece.msstate.edu/

Digital System - http://www.ece.msstate.edu/~reese/EE4743/

List of lectures - http://www.ece.msstate.edu/~reese/EE4743/lectures/

Lecture's on VLSI (Video)

Hope it will be useful to understand VLSI basics, it is a IIT lecture.

Click on me

Here are some useful links for VLSI professional's

http://jab-semi.blogspot.com/

http://iccoach.blogspot.com/

http://theasicguy.com/

http://asicdigitaldesign.wordpress.com/

http://chipverification.blogspot.com/

http://digitalelectronics.blogspot.com/

http://www.specman-verification.com/index.php

http://fpgacomputing.blogspot.com/

http://digital-ic-design.blogspot.com/

http://chipdesignart.wordpress.com/

http://vlsifaq.blogspot.com/

http://asictao.blogspot.com/

http://www.coolverification.com/

http://www.thinkverification.com/

http://www.dftdigest.com/

http://ninjaverification.wordpress.com/

http://www.srikiran.net/blog

http://digitalverification.blogspot.com/

http://cad-for-vlsi.blogspot.com/

http://embeddedsystemdesign.blogspot.com/

http://freedft.info/

http://www.asic-soc.blogspot.com/

http://www.deepchip.com/

http://www.vlsichipdesign.com/

http://www.edaboard.com/

http://electrosofts.com/

http://www.fpgacentral.com/

http://www.fpgaseek.com/

http://main.semiconductorforums.com/

http://www.soccentral.com/

http://www.vlsiip.com/

VLSI Tools Demo

Demos on Demand (Click the link)

Points and topics to be covered before an interview

This post will be updated further......
Post your valuable comments

Read Basic electronics and digital concepts
Combinational circuits (Basic gates, Mux, Adder, Multiplier and Encoder ...)
Sequential circuits (Latch, Flip flop, State machine and Counter ...)
Memories (Single, Dual, Quad port RAM and ROM)
MOS, CMOS, NMOS and PMOS techniques

Read all Cliff Cummings free papers

Read about Verilog language
Diff b/w tasks and functions
Diff b/w blocking and non blocking
Diff b/w various delays
Full and Parallel case
Diff b/w casex and casez
Diff b/w === and ==
Diff b/w logical && and bitwise &
Diff b/w bitwise, unary, logical operators
Diff b/w blocking and non blocking operator
Diff b/w always and initial
Diff b/w procedural and continuous assignment
Can task/function is synthesizable?
Can for/repeat/while loop is synthesizable?
Can fork join is synthesizable?


Read about VHDL language
Diff b/w signals and variables
Diff b/w functions and procedures

Read RMM Guidelines

Read synthesis concepts

Read Timing simulation and techniques

Read below listed concepts and topics
Clock dividers
Reset synchronizer
Clock and Reset tree
Clock Skew, Clock fidelity, Clock Jitter
Cross talk
Synchronization techniques - Handshake, Double flop, Three flop, Pulse, Level and FIFO based
DFT
BIOS
BIST
Timing
CPLD, FPGA and ASIC
FIFO and RAM
Gate level netlist
SDF
Low power design techniques
Pipe line design
Static and Dynamic timing analysis
FIFO depth calculation
Setup and Hold time, Clock to Q, Pin-to-pin and propagation delay
Metastability
Maximum frequency formula
Inertial, Transport and various delays
Mealy and Moore FSM
Binary and One hot encoding
Binary and Gray pointers
Master and Slave DMA
Arbitration techniques – Round robin, Weighted Round robin, Programmable weighted round robin, Priority, Circular etc.,
Various timing delays
Synchronous and Asynchronous clocks
Synchronous and Asynchronous resets
Latch and Flop
Multi cycle and False path
Glue logic
PLL

General technical questions
How will you start code a RTL?
What are the general coding guide lines/styles you followed?
Tell us the tools you have been working?
How your test environment looks?
Once you have done the RTL code, does your work end? What will you do next?

Read PERL language

Read PLI generation and usage

Read all the Tools and Analyzers you worked

Read all the protocol specifications you are in familiar
List out the important terms and points in the specifications

Take care of the below designs
Multi clock design
FIFO design
Various RAMs

General questions asked by an interviewer
Tell us about your self
Tell us about your current project
Which one you are interested in? Design or Verification?
Have you involved in verification?
Why are you leaving the current company?
What is your expected salary?
Do you have any offers from other company?
Are you actively participating this interview?
Are you ready to relocate to our company located in “SOME” place?
Do you have any questions?